Back to Hack Nights Spring 2018 co-hosted with ACV Auctions

Custom RISC CPU, Assembler, and Simulator Hack Nights Spring 2018 co-hosted with ACV Auctions

Running for:
Best Design
Best Hardware Hack
Most Polished Hack


Repository https://github.com/ZacharySalim/Smallpond

In a collaboration for CSE 443 Compilers and CSE 490 Computer Architecture, the reduced instruction set architecture Smallpond has been born, and a toolchain for the ISA has been built. It has now been implemented on the Digilent Basys 3 FPGA development board with gdb debug, and a flexible assembler and simulator framework has been written in Java which allows for quick changes to the ISA. In fact, with the redefinition of a few classes, an entirely new ISA can be created and simulated with this Java program. Features of the processor: gdb-like debug, memory mapped IO, UART connectivity, interesting special purpose registers.

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